1. Field of the Invention
The present invention relates to a logic circuit apparatus which utilizes a programmable logic circuit capable of changing a function to be realized during operation of the programmable logic circuit.
2. Description of the Related Art
In an integrated circuit including a plurality of circuits which correspond to certain processing steps, the processing speed of the integrated circuit is defined based on the step requiring the most throughput. However, since some steps only require low throughput, the entire integrated circuit provides excessively high throughput.
A programmable logic circuit is proposed that can change its circuit configuration and its function during operation. The programmable logic circuit can change either an overall circuit or a partial circuit configuration.
An example of the programmable logic circuit is a field programmable gate array (FPGA) configured to change its circuit configuration quickly. A field programmable gate array will be simply referred to as a “programmable logic circuit” hereinafter.
A conventional method of time-sharing of a programmable logic circuit is disclosed in Japanese Patent Publication (KOKAI) No. 2001-202236. In this method, in response to throughput required by each of the steps, a time distribution for processing of the respective steps is predetermined. The circuit configuration of the programmable logic circuit is changed in accordance with the time distribution.
In this method, the time distribution must be predetermined in such a manner that the processing time for the steps requiring high throughput is prolonged, whereas the processing time for the steps requiring low throughput is shortened. Therefore, the processing times cannot be properly allocated in correspondence with the dynamic changes in the throughput which is required by the respective steps.